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Condor Currents

Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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  • 67 episodes
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Episodes 67

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  • July 27 · length unknown

    TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters

    ## Episode Summary In this episode, we cover: - **TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters** (arXiv) - **Black-Box Performance Evaluation of Elastic Block Storage: Contract, Rate-Limiting Model, and Software Exploration** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - AOL.com** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

  • July 26 · length unknown

    DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

    ## Episode Summary In this episode, we cover: - **DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis** (arXiv) - **Isolation Failure From Shared Storage: Characterizing and Exploiting Page-Cache SCA Leakage Across Containers and VMs** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) --- *Sponsored by AIEDA, Ago Consulting, and Zen Semiconductor*

  • July 25 · length unknown

    RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse

    ## Episode Summary In this episode, we cover: - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **AMD Zen 7 “2028” and Zen 8 “2030” CPU Architectures Confirmed – EPYC Florence “Zen 7” To Feature Next-Gen Node, & ACE Extensions - Wccftech** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 24 · length unknown

    AMD reveals CPU architecture roadmap through 2028, following Zen 6 'Venice' launch — Zen 7 'Florence' to de... - Yahoo Tech

    ## Episode Summary In this episode, we cover: - **AMD reveals CPU architecture roadmap through 2028, following Zen 6 'Venice' launch — Zen 7 'Florence' to de... - Yahoo Tech** (google_arch) - **AMD Zen 7 “2028” and Zen 8 “2030” CPU Architectures Confirmed – EPYC Florence “Zen 7” To Feature Next-Gen Node, DDR6 Memory & ACE Extensions - Wccftech** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 22 · length unknown

    NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist

    ## Episode Summary In this episode, we cover: - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors** (semiengineering) - **HW-based Methods to Dynamically Throttle AI Performance (Princeton University)** (semiengineering) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) - **Buet tapes out open-source 32-bit RISC-V processor 'Pragati v1' - The Business Standard** (google_riscv) --- *Sponsored by LimitLess AI*

  • July 21 · length unknown

    SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

    ## Episode Summary In this episode, we cover: - **SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput** (arXiv) - **Inter-Set Correlation-Aware Replacement Policy for Energy Efficient RTM-based Caches** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by LimitLess AI*

  • July 20 · length unknown

    DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction

    ## Episode Summary In this episode, we cover: - **DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction** (arXiv) - **StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence** (arXiv) - **RISC-V Milk-V Jupiter 2 SBC Benchmarked: 60 TOPS NPU and SiFive K3 SoC - Geeky Gadgets** (google_riscv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --- *Sponsored by LimitLess AI*

Showing 61–67 of 67 episodes