Condor Currents

Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Today · length unknown
FORGE: Procedural Weight Generation for Sparse MoE Inference
## Episode Summary In this episode, we cover: - **FORGE: Procedural Weight Generation for Sparse MoE Inference** (arXiv) - **AlignPred: Error-Controlled KV Cache Compression via Alignment and Predictive Coding** (arXiv) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU - alphaXiv** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Yesterday · length unknown
Foundations of Hardware-Software Leakage Contracts
## Episode Summary In this episode, we cover: - **Foundations of Hardware-Software Leakage Contracts** (arXiv) - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Friday · length unknown
Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!
## Episode Summary In this episode, we cover: - **Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!** (arXiv) - **Minimum RISC-V: Maximum FPGA Efficiency** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Thursday · length unknown
TALU: A Reconfigurable Tiled-ALU Grid for RISC-V
## Episode Summary In this episode, we cover: - **TALU: A Reconfigurable Tiled-ALU Grid for RISC-V** (arXiv) - **CacheSmith: Accurate RAG Serving under Latency SLOs with Adaptive KV Reuse** (arXiv) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **Meta’s Muse AI Agent Just Designed A Crypto-Specific SoC On The RISC-V Architecture For $2,000 To Transform The Thru Blockchain Into “The Fastest On Earth” - Wccftech** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Wednesday · length unknown
Programmable Data Layouts via On-The-Fly Data Transformation
## Episode Summary In this episode, we cover: - **Programmable Data Layouts via On-The-Fly Data Transformation** (arXiv) - **Simulate Before You Scale: High-Fidelity LLM Inference Planning Without GPUs** (arXiv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Tuesday · length unknown
Read What Matters: Query-Adaptive Quantization for KV Caches
## Episode Summary In this episode, we cover: - **Read What Matters: Query-Adaptive Quantization for KV Caches** (arXiv) - **A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Monday · length unknown
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
## Episode Summary In this episode, we cover: - **CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support** (arXiv) - **Taking Tokenization off the Host for Agentic LLM Serving** (arXiv) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **What Is a Microarchitecture? Understanding Processors and Register Files in an ARM Core - All About Circuits** (google_arch) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 11 · length unknown
A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
## Episode Summary In this episode, we cover: - **A Framework for Accelerating Transformer Inference on RISC-V for Edge AI** (arXiv) - **ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the RISC-V Architecture - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 10 · length unknown
SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
## Episode Summary In this episode, we cover: - **SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS** (arXiv) - **BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks** (arXiv) - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv) - **Efinix® Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire™ RV64 SoC - Yahoo Finance** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 9 · length unknown
CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies
## Episode Summary In this episode, we cover: - **CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies** (arXiv) - **CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation** (arXiv) - **Nuvia’s Architects Now Preparing a CPU for Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 8 · length unknown
CHiRP: Control-Flow History Reuse Prediction
## Episode Summary In this episode, we cover: - **CHiRP: Control-Flow History Reuse Prediction** (arXiv) - **SVRF: Efficient Register Storage for Long-Vector Architectures** (arXiv) - **WheatForce: Learning From CPU Architecture Mistakes - Hackaday** (google_arch) - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv) - **RISC-V Processor Advances Local Chip Design - Open Source For You** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 7 · length unknown
Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas
## Episode Summary In this episode, we cover: - **Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas** (arXiv) - **CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency** (arXiv) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - www.embedded.com** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 6 · length unknown
Characterizing High Bandwidth Flash for LLM Serving
## Episode Summary In this episode, we cover: - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv) - **Request Order Matters: Cache-History Sensitivity in Selective KV-Cache Reuse for Rolling Agents** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) - **Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver - XDA** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - embeddedcomputing.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 5 · length unknown
ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration
## Episode Summary In this episode, we cover: - **ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration** (arXiv) - **AdaptViT: Runtime-Adaptive Vision Transformer Deployment on Custom RISC-V** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC for FPGA-Based Embedded Systems - EE Times Asia** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 4 · length unknown
Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding
## Episode Summary In this episode, we cover: - **Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding** (arXiv) - **U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - spectrum.ieee.org** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - cnx-software.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 3 · length unknown
Efficient Linkage-Based Compartmentalization on CHERI
## Episode Summary In this episode, we cover: - **Efficient Linkage-Based Compartmentalization on CHERI** (arXiv) - **SPIMOE: Exploiting Hybrid Sparsity for Reasoning MoE Inference on Heterogeneous PIM Architectures** (arXiv) - **HBF for High-Throughput LLM Serving (UC Berkeley, FuriosaAI)** (semiengineering) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 2 · length unknown
Characterizing High Bandwidth Flash for LLM Serving
## Episode Summary In this episode, we cover: - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv) - **STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
October 1 · length unknown
Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders
## Episode Summary In this episode, we cover: - **Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders** (arXiv) - **DPS: Dual-Mode Precision LLM Serving with Semi-Unified Memory** (arXiv) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - wccftech.com** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 30 · length unknown
Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6
## Episode Summary In this episode, we cover: - **Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6** (arXiv) - **Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 29 · length unknown
QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society
## Episode Summary In this episode, we cover: - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64 - The Futurum Group** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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