Condor Currents

Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Yesterday · length unknown
Characterizing High Bandwidth Flash for LLM Serving
## Episode Summary In this episode, we cover: - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv) - **Request Order Matters: Cache-History Sensitivity in Selective KV-Cache Reuse for Rolling Agents** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) - **Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver - XDA** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - embeddedcomputing.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Monday · length unknown
ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration
## Episode Summary In this episode, we cover: - **ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration** (arXiv) - **AdaptViT: Runtime-Adaptive Vision Transformer Deployment on Custom RISC-V** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC for FPGA-Based Embedded Systems - EE Times Asia** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Sunday · length unknown
Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding
## Episode Summary In this episode, we cover: - **Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding** (arXiv) - **U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - spectrum.ieee.org** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - cnx-software.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Saturday · length unknown
Efficient Linkage-Based Compartmentalization on CHERI
## Episode Summary In this episode, we cover: - **Efficient Linkage-Based Compartmentalization on CHERI** (arXiv) - **SPIMOE: Exploiting Hybrid Sparsity for Reasoning MoE Inference on Heterogeneous PIM Architectures** (arXiv) - **HBF for High-Throughput LLM Serving (UC Berkeley, FuriosaAI)** (semiengineering) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - embedded.com** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs - Embedded Computing Design** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Friday · length unknown
Characterizing High Bandwidth Flash for LLM Serving
## Episode Summary In this episode, we cover: - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv) - **STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
Thursday · length unknown
Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders
## Episode Summary In this episode, we cover: - **Cache-Aware Conv3D Lowering Across Embedded World-Model Decoders** (arXiv) - **DPS: Dual-Mode Precision LLM Serving with Semi-Unified Memory** (arXiv) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - wccftech.com** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 30 · length unknown
Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6
## Episode Summary In this episode, we cover: - **Bandwidth, Not FLOPS: FFT Kernels, Matrix Units and SAR Imaging on Apple M6** (arXiv) - **Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 29 · length unknown
QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society
## Episode Summary In this episode, we cover: - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64 - The Futurum Group** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 28 · length unknown
The KV Cache Is the New Memory Wall
## Episode Summary In this episode, we cover: - **The KV Cache Is the New Memory Wall** (arXiv) - **PipeDRAM: A Data-Transposition-Free In-DRAM Architecture with Hardware/Software Pipelining** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 27 · length unknown
HeteroReason: Heterogeneous FPGA-GPU Acceleration for Disaggregated Speculative Reasoning
## Episode Summary In this episode, we cover: - **HeteroReason: Heterogeneous FPGA-GPU Acceleration for Disaggregated Speculative Reasoning** (arXiv) - **SARA: SLO-Aware Resource Allocation for Disaggregated Agentic LLM Services** (arXiv) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - HPCwire** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 26 · length unknown
Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs
## Episode Summary In this episode, we cover: - **Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs** (arXiv) - **Paging the Experts: A Reproducible Characterization of Flash-Backed MoE Inference on iPhone** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 25 · length unknown
Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management
## Episode Summary In this episode, we cover: - **Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management** (arXiv) - **HBF-Sim: An Extensible HBF Simulator for Large-scale GPU Memory Systems** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC - HPCwire** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 19 · length unknown
PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving
## Episode Summary In this episode, we cover: - **PrefixBench-H100: Characterizing Prefix Reuse and Time-to-First-Token in H100 LLM Serving** (arXiv) - **Understanding and Exploiting Diagonal Attention Sparsity in Autoregressive Image Generation** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Kari Hepola: Custom tools make RISC-V processors faster and easier to design - tuni.fi** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - semiengineering.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 18 · length unknown
RISC-V and machine learning: a survey
## Episode Summary In this episode, we cover: - **RISC-V and machine learning: a survey** (arXiv) - **MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators** (arXiv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch) - **nRF54LC10A SoC features Cortex-M33, RISC-V coprocessor, Bluetooth LE, Thread and Zigbee - LinuxGizmos.com** (google_riscv) - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 17 · length unknown
Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator
## Episode Summary In this episode, we cover: - **Quantifying the Effect of HCLs on a Fixed-Microarchitecture MXFP4 Accelerator** (arXiv) - **HBFlex: A Flexible Memory System for Bridging Fine-Grained LLM States and Coarse-Grained HBF Parallel Execution** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - nature.com** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Platform: A Custom RISC-V CPU - Hackster.io** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 16 · length unknown
The World Model Hardware Accelerator
## Episode Summary In this episode, we cover: - **The World Model Hardware Accelerator** (arXiv) - **A 25-$μ$s/inf Event-driven Graph Neural Network Processor with Spatiotemporal Caching and Spline Convolution for Ultra-low-latency AI at the Edge** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - chinadaily.com.cn** (google_arch) - **Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver - XDA** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 15 · length unknown
BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference
## Episode Summary In this episode, we cover: - **BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference** (arXiv) - **Arborist: Algorithm-Hardware Co-Design for Fast and Efficient Motion Planning** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **SiFive RISC-V is an Open-Source Processor! - ServeTheHome** (google_riscv) - **RISC-V Processor Advances Local Chip Design - Open Source For You** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 13 · length unknown
India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com
## Episode Summary In this episode, we cover: - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) - **StarFive Dubhe-100 – A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX Software** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 12 · length unknown
Enabling High-Bandwidth Flash for Generative Recommendation Serving with Write-Aware KV Cache Policy
## Episode Summary In this episode, we cover: - **Enabling High-Bandwidth Flash for Generative Recommendation Serving with Write-Aware KV Cache Policy** (arXiv) - **Sharing a Fabric with Collective Communication: Two Storage Penalties in Deep Learning Training** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eenewseurope.com** (google_riscv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - techpowerup.com** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
September 11 · length unknown
HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments
## Episode Summary In this episode, we cover: - **HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments** (arXiv) - **Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

Showing 1–20 of 70 episodes