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Condor Currents · Yesterday

SPEC CPU2026 Under the Microscope: Programs, Phases, and Samples

## Episode Summary In this episode, we cover: - **SPEC CPU2026 Under the Microscope: Programs, Phases, and Samples** (arXiv) - **LLMRunner: Closed Workload Model Performance Testing Framework for LLM Servings** (arXiv) - **Embedding RISC-V CPU Directly into AI Weights: Qwen3.5-4B-Based "Qwenputer" Released - finance.biggo.com** (google_riscv) - **DAMO Academy's XuanTie XL-300 Interconnect IP Links Up to Eight RISC-V Cores With 32MB of L3 - Pandaily** (google_riscv) - **AI agent designs RISC-V processor in 12 hours from 219-word specification - Mezha** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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## Episode Summary
In this episode, we cover:
- **SPEC CPU2026 Under the Microscope: Programs, Phases, and Samples** (arXiv)
- **LLMRunner: Closed Workload Model Performance Testing Framework for LLM Servings** (arXiv)
- **Embedding RISC-V CPU Directly into AI Weights: Qwen3.5-4B-Based "Qwenputer" Released - finance.biggo.com** (google_riscv)
- **DAMO Academy's XuanTie XL-300 Interconnect IP Links Up to Eight RISC-V Cores With 32MB of L3 - Pandaily** (google_riscv)
- **AI agent designs RISC-V processor in 12 hours from 219-word specification - Mezha** (google_riscv)
---
*Sponsored by Ada, Ago Consulting, and Zen Semiconductor*

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